/*Yipeng Huang and Scott Rogowski*/
/*yh2315 smr2167*/

//Simple 5 bit to 32 wire decoder.
module Decoder (decoder_in, decoder_out);

	input [4:0] decoder_in;
	output [31:0] decoder_out;
	reg [31:0] mid;
	
	always @(*) begin
		case(decoder_in)
			5'd0:   mid = 32'b00000000000000000000000000000001;
			5'd1:   mid = 32'b00000000000000000000000000000010;
			5'd2:   mid = 32'b00000000000000000000000000000100;
			5'd3:   mid = 32'b00000000000000000000000000001000;
			5'd4:   mid = 32'b00000000000000000000000000010000;
			5'd5:   mid = 32'b00000000000000000000000000100000;
			5'd6:   mid = 32'b00000000000000000000000001000000;
			5'd7:   mid = 32'b00000000000000000000000010000000;
			5'd8:   mid = 32'b00000000000000000000000100000000;
			5'd9:   mid = 32'b00000000000000000000001000000000;
			5'd10:  mid = 32'b00000000000000000000010000000000;
			5'd11:  mid = 32'b00000000000000000000100000000000;
			5'd12:  mid = 32'b00000000000000000001000000000000;
			5'd13:  mid = 32'b00000000000000000010000000000000;
			5'd14:  mid = 32'b00000000000000000100000000000000;
			5'd15:  mid = 32'b00000000000000001000000000000000;
			5'd16:  mid = 32'b00000000000000010000000000000000;
			5'd17:  mid = 32'b00000000000000100000000000000000;
			5'd18:  mid = 32'b00000000000001000000000000000000;
			5'd19:  mid = 32'b00000000000010000000000000000000;
			5'd20:  mid = 32'b00000000000100000000000000000000;
			5'd21:  mid = 32'b00000000001000000000000000000000;
			5'd22:  mid = 32'b00000000010000000000000000000000;
			5'd23:  mid = 32'b00000000100000000000000000000000;
			5'd24:  mid = 32'b00000001000000000000000000000000;
			5'd25:  mid = 32'b00000010000000000000000000000000;
			5'd26:  mid = 32'b00000100000000000000000000000000; 
			5'd27:  mid = 32'b00001000000000000000000000000000; 
			5'd28:  mid = 32'b00010000000000000000000000000000;
			5'd29:  mid = 32'b00100000000000000000000000000000;
			5'd30:  mid = 32'b01000000000000000000000000000000;
			5'd31:  mid = 32'b10000000000000000000000000000000;
		endcase
	end
	
	assign decoder_out = mid;
	
endmodule
